Counters are conventionally used in virtually every digital circuit design and implementation. In such conventional counter circuits, when the counter count reaches a target value, a terminal count output is typically generated. This terminal count output is then used to trigger other events in the digital circuit.
We now identify certain notational conventions that will be used to describe conventional counter structure and method as well as the inventive counter structure and method in subsequent sections of this disclosure. For an n-bit wide signal or signal value, the most significant bit is the bit designated as bit (n-1), and the least significant bit is the bit designated bit 0. We note that in general, a signal can have different values at different times. The term "name [index]" refers to bit number index of the signal identified as name, so that for example, we refer to "trigger[3]" as bit 3 of the trigger signal. The term "name [index1:index2]" represents all bits from bit number index1 to bit number index2 inclusive of the signal called "name".
A conventional counting procedure 100 and the steps a conventional counter such as counter 10 in FIG. 2, executes is now described relative to the diagrammatic flow-chart in FIG. 1 and the digital circuit diagram in FIG. 2. In Step 101, an n-bit wide flip-flop array 11 within counter 10 waits for an active clock input signal (CLK.sub.-- IN) edge. When the clock edge is detected, the counter output signal CNT generated at the Q output of flip-flop array 11 is set to 0 if the terminal count output TC is 1 (Step 102), and otherwise CNT is set to ADD.sub.-- OUT (Step 104), where ADD.sub.-- OUT is the output generated by n-bit adder 14. Terminal count output TC is generated from TERM.sub.-- CNT and CNT in counter 10, and will be zero ("0") when TERM.sub.-- CNT and CNT are not equal, and one ("1") when TERM.sub.-- CNT is equal to CNT.
In Step 105, CNT is compared in the n-bit wide comparator 13 with the terminal count value TERM.sub.-- CNT. The terminal count value TERM.sub.-- counter 10. Individual bits of TERM.sub.-- CNT may alternatively be hard wired to particular "1" or "0" logic levels or voltages representing these logic states. When TERM.sub.-- CNT is equal to CNT, TC is set to 1 (Step 106); when they are not equal, TC remains 0 (Step 107). Finally in Step 108, the adder 14 output signal ADD.sub.-- OUT is set to the value of CNT incremented by one value (CNT+1), and the method 100 begins again waiting for an active clock edge (Step 101). From this description of a conventional digital counter, it is clear that the comparisons are n-bit wide bit-by-bit comparisons.
C N T   i s   g e n e r a t e d ,   c o m p u t e d ,   s t o r e d   i n   a   r e g i s t e r ,   o r   o t h e r w i s e   p r o v i d e d   t o
We now describe a typical conventional digital logic circuit implementation of the method in FIG. 1 relative to counter 10 in FIG. 2. This implementation is especially common in ASIC or cell-based design environment, because all of the counter 10 components are readily available in cell libraries, and because it can be clearly described to synthesis tools in Hardware Design Language (HDL). Counter 10 consists of one n-bit wide comparator 13 which performs steps 105, 106, and 107; one n-bit wide flip-flop array 11 and one n-bit wide 2-to-1 multiplexer 15. Comparator 13, flip-flop array 11, and multiplexer 15 together carry out steps 101, 102, 103, and 104. Counter 10 also includes an n-bit adder 14 which performs the addition procedure in Step 108. The variable n is determined by the width of the terminal count value TERM.sub.-- CNT, that is by the number of bits required to represent the terminal count value. Of course a greater number of bits may be used than the number actually required.
At the rising edge of every clock CLK.sub.-- IN 11b (Step 101), the D input 11a of flip-flop array 11 is transferred to its Q output 11c (Step 103 or Step 104). Q output 11c is connected to the count output CNT. Q output 11c is also connected to input 14a of adder 14, whose second input 14b is coupled to the structure storing or repesenting constant 1. Note that in this description, reference to a register storing a variable, parameter, constant, or the like is understood to mean not only a storage register, but also any other means for representing that value, such as for example, representing that value by actually storing the value in a register, memory, or other storage means, connecting it to a predetermined voltage level representing a logic value, connecting it to a circuit that generates the logic value, or the like implementations. In the case of a constant 1 for example, the second input 14b may be connected or hard-wired to a voltage representing logic value "1". Adder output 14c, which during normal operation within the operating range of the counter, is always one greater than Q output 11c (Step 108), is connected to the Data0 (D0) input 15a of the multiplexer 15. (It may be noted that once the design limit of the counter is reached, for example at a count of 15 in a 4-bit counter, then the adder output 14c may not be greater than the Q output 11c, but we generally don't care about the adder output 14c once the counter output reaches its maximum count, in this case at a count of 15.) The Data1 (D1) input 15b of the multiplexer is wired to a register or logic element storing or representing the constant 0, hardwired to a voltage level representing logic level "0". It may also be noted that typically, constants are usually hard-wired rather than stored in a register or other storage means.
The flip-flop array Q output 11c is also fed to comparator 13 through the "A" input 13a. This comparator compares the "A" input (flip-flop Q output) 13a with the target count TERM.sub.-- CNT value 13b. When input 13a is not equal to the "B" comparator input 13b, the comparator output 13c is 0; when they are equal, comparator output 13c (terminal count output TC), becomes 1 (Steps 105, 106, and 107).
In addition to signaling the terminal count, comparator output 13c also provides a control (input select) signal to multiplexer 15 through its select input at terminal 15d. When terminal 15d is logic 0, the multiplexer passes the input appearing at terminal 15a to its Y output terminal 15c (Steps 102 and 103). When select terminal 15d is logic 1, the signal at terminal 15b is passed through multiplexer 15 and appears at the Y output terminal 15c (Steps 102 and 104) as the MUX.sub.-- OUT signal. Since multiplexer output terminal 15c is connected to flip-flip array 11 "D" input 11a, at the next rising clock edge, counter 10 will either be reset to 0 if TC is 1, or continue to count toward the next count if TC is 0.
The timing diagram showing the relationships between and among the CLK.sub.-- IN, CNT, TC, ADD.sub.-- OUT, and MUX.sub.-- OUT signals of the operation of conventional counter 10 is shown in FIG. 3. This timing diagram covers a period surrounding the assertion of TC.
As describe previously earlier, all counter 10 components in FIG. 2 are n-bit wide, and the particular value of n is determined by the value of TERM.sub.-- CNT. The reason for the width requirement is that the all components must be at least as wide as the greatest possible TERM.sub.-- CNT. For example, if the range of TERM.sub.-- CNT is from 13 to 137, then all components must be at least 8-bit wide in order to represent 137, because at some point CNT will be equal to TERM.sub.-- CNT, as shown in FIGS. 1 and 2. Recall that decimal 137 is binary 10001001 requiring 8 bits. The counter output signal (CNT) will require 8 bits for proper representation when CNT reaches and is equal to TERM.sub.-- CNT. This means all counter 10 components must be 8-bit wide to handle 8-bit quantities. (Although wider components can be used, they are not needed and will only consume area and power.)